1. Field of the Invention
The present invention relates to semiconductor devices and a method for fabricating them and, more particularly, to a method for fabricating DRAM (Dynamic Random Access Memory) cell capacitors that can be used in high-density integrated circuits.
2. Description of the Related Art
As the cell density of DRAM devices increases, there is a continuous need to maintain a sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuous need to further reduce the cell area. In order to keep the capacitance of storage capacitors in DRAMs at an acceptable value, many methods have been studied and developed. One approach is to use a film with a high dielectric constant such as BST (barium strontium titanate) for the storage electrode in the capacitors instead of conventional NO (Nitride Oxide) or ONO (Oxide Nitride Oxide) dielectric films. The use of high-dielectric-constant films, however, is still being studied and tested and there are problems relating to reliability.
An alternative approach is to form three dimensional capacitors such as stacked capacitors in order to increase available surface area. Such stacked capacitors include, for example, double-stacked, fin stacked, cylindrical, spread-stacked, or box structure capacitors.
Because both outer and inner surfaces of a cylindrical capacitor can be utilized as effective capacitor ares, the cylindrical structure is favorable for integrated circuit memory cells such as DRAM cells among the three-dimensional stacked capacitors.
U.S. Pat. No. 5,340,765 (issued on Aug. 23, 1994) discloses a method for fabricating a capacitor structure resembling a cylindrical container. U.S. Pat. No. 5,340,763 (issued on Aug. 23, 1994) discloses more complex structures, such as the container-within container and multiple pin structures.
Recently, new technologies have been developed for further increasing the effective surface area of DRAM cells by modifying the surface morphology of the polysilicon storage node itself. This is accomplished by engraving or controlling the nucleation and growth condition of polysilicon. A hemispherical grain (HSG) silicon layer can be deposited over a storage node to increase surface area and capacitance.
One problem associated with a capacitor having a HSG silicon layer is the formation of electrical bridges between adjacent storage nodes. Furthermore, high density DRAM devices leave only a little space for the storage nodes of a memory cell, making it difficult to employ HSG silicon in the inner surface of cylindrical capacitors and resulting in electrical bridges between opposite HSG silicon layers within the cylinder, particularly with respect to the shortest direction of cylindrical capacitors.
More specifically, in 256M DRAMs of a 170 nm design rule, a cylindrical capacitor with a HSG silicon layer has a minimum feature size of 170 nm in the shortest direction. At this time, a HSG frame conductive layer is required be at least 40 nm thick, and a HSG is about 30 nm thick. The overall thickness of the storage node having a HSG silicon layer becomes about 140 mn. Because a dielectric film is about 8 nm thick and a plate node is about 30 nm thick, it is very different to form a dielectric film and a plate node subsequently. That is, the overall dimension of layers deposited in the cylindrical opening in the shortest direction is about 216 nm, which exceeds the design rule of 170 nm. Accordingly, it has heretofore been impossible to form a HSG silicon layer in compliance with a design rule of 170 mn.